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SN74SSTU32864 Arkusz danych(PDF) 8 Page - Texas Instruments

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Numer części SN74SSTU32864
Szczegółowy opis  25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS
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SN74SSTU32864 Arkusz danych(HTML) 8 Page - Texas Instruments

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SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TERMINAL FUNCTIONS
TERMINAL NAME
DESCRIPTION
ELECTRICAL
CHARACTERISTICS
GND
Ground
Ground input
VCC
Power-supply voltage
1.8 V nominal
VREF
Input reference voltage
0.9 V nominal
CLK
Positive master clock input
Differential input
CLK
Negative master clock input
Differential input
C0, C1
Configuration control inputs – Register A, Register B, 1:1, 1:2 select
LVCMOS inputs
RESET
Asynchronous reset input – resets registers and disables VREF data and clock
differential-input receivers
LVCMOS input
D1–D25
Data inputs – clocked in on the crossing of the rising edge of CLK and the falling edge of
CLK
SSTL_18 inputs
CSR, DCS
Chip select inputs – disables D1-D25† outputs switching when both inputs are high
SSTL_18 inputs
DODT
The outputs of this register bit will not be suspended by the DCS and CSR control.
SSTL_18 input
DCKE
The outputs of this register bit will not be suspended by the DCS and CSR control.
SSTL_18 input
Q1–Q25‡
Data outputs that are suspended by the DCS and CSR control
1.8 V CMOS outputs
QCS
Data output that will not be suspended by the DCS and CSR control
1.8 V CMOS output
QODT
Data output that will not be suspended by the DCS and CSR control
1.8 V CMOS output
QCKE
Data output that will not be suspended by the DCS and CSR control
1.8 V CMOS output
NC
No internal connection
DNU
Do not use – inputs are in standby-equivalent mode, and outputs are driven low.
† Data inputs = D2, D3, D5, D6, D8–D25 when C0 = 0 and C1 = 0
Data inputs = D2, D3 D5, D6, D8–D14 when C0 = 0 and C1 = 1
Data inputs = D1–D6, D8–D10, D12, D13 when C0 = 1 and C1 = 1.
‡ Data outputs = Q2, Q3, Q5, Q6, Q8–Q25 when C0 = 0 and C1 = 0
Data outputs = Q2, Q3 Q5, Q6, Q8–Q14 when C0 = 0 and C1 = 1
Data outputs = Q1–Q6, Q8–Q10, Q12, Q13 when C0 = 1 and C1 = 1.


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